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? semiconductor ml7005 1/24 ? semiconductor ml7005 dtmf transceiver general description the ml7005 is a multi-functional dtmf transceiver lsi with built-in a dtmf signal generator, a dtmf signal receiver, a call progress tone generator, a call progress tone detector, and a fax (fx) signal detector. each functional block can be controlled by an external mcu via a 4-bit processor interface. the ml7005 does not contains a modem. however, the dtmf system data transmission is possible at less than 66 bps by setting the dtmf receiver to the high-speed detection mode. the ml7005 operates with low-power consumption and is suitable for remote control systems, especially for acr (automatic cost routing) controllers. features ? wide range of power supply voltage : +2.7 v to +5.5 v ? low power consumption operating mode : 4.0 ma (v dd = 3 v) typ. operating mode : 5.0 ma (v dd = 5 v) typ. power down mode : 1 m a typ. ? the 4-bit processor interface supports both the intel processor mode in which a read signal and a write signal are used independently of each other, and the motorola processor mode in which a read signal and a write signal are used in common. ? the dtmf receiver can select either the high-speed detection mode (signal repeat time: more than 60 ms) or the normal detection mode (signal repeat time: more than 90 ms). ? built-in call progress tone generator ? built-in fax signal (fx: 1300 hz) detector ? the dtmf signal generator, dtmf signal detector, call progress tone generator, and call progress tone detector can operate concurrently. ? built-in 3.579545 mhz crystal oscillator circuit ? package : 32-pin plastic ssop (ssop32-p-430-1.00-k) (product name: ml7005mb) e2a0050-29-81 this version: aug. 1999 previous version: may 1999
? semiconductor ml7005 2/24 block diagram C + pre lpf fx detector fxdim fxdio + C pre lpf cpt detector cpdip cpdio cpdim + C pre lpf dtmf receiver dtrip dtrio dtrim C + lpf dtmf generator dtai dtao dtgo cpt generator C + cpai cpao sg generator sg v dd gnd status register ptype d0 d1 d3 d2 wr read ale cs control register fxd0 cpd0 x1 x2 clko pd processor interface cptgo
? semiconductor ml7005 3/24 pin configuration (top view) 32-pin plastic ssop 17 wr 32 cpdio 31 cpdim 30 cpdip 29 fxdio 28 fxdim 27 fxdo 26 dtao 25 dtai 24 dtgo 23 gnd 22 cpdo 21 d0 20 d1 19 d2 18 d3 16 ale 1 dtrio 2 dtrim 3 dtrip 4 sg 5 cpao 6 cpai 7 cptgo 8 ptype 9 v dd 10 pd 11 x1 12 x2 13 clko 14 read 15 cs
? semiconductor ml7005 4/24 pin description pin symbol type description 1o dtrio output pin for dtmf signal receiver input amplifier. see the figure 8 for adjusting the receive signal level. see the figure 10 when the dtmf signal receiver is not used. 2i dtrim inverting input pin for dtmf signal receiver input amplifier. 3i dtrip non-inverting input pin for dtmf signal receiver input amplifier. 4o sg output pin for signal ground. the output voltage is half of v dd . connect sg and gnd by a 1 f capacitor. this pin goes to a high impedance state when in power down mode. 5o cpao output pin for amplifier used for adjusting the transmit output level of cpt (call progress tone) signal generator. the non-inverting input of this amplifier is internally connected to sg. see the figure 11 for adjusting the transmit signal level. when this amplifier is not used, the cpao pin should be shorted to the cpai pin. 6i cpai inverting input pin for amplifier used to adjust the transmit level of the cpt signal generator. 7o cptgo analog output pin for cpt signal generator. the tone amplitude is approximately - 3 dbm. the transmit signal level can be changed by using the cpao and cpai pins. see the figure 11 for adjusting the transmit signal level. control the on/off of cpt transmission by using cpgc of the control register. 8i ptype input pin for selecting the processor mode. this selection determines the functions of read , cs , ale, wr , d1 and d0 pins. when this pin is "1", the intel processor mode is selected. when this pin is "0", the motorola processor mode (msm7524-compatible) is selected. this pin should be fixed at "0" or "1". 9 v dd power supply pin. 10 i pd input pin for controlling the power down mode. when this pin is set to "1", the entire lsi enters the power down mode and each functional operation stops. the dc level of the analog output pin becomes undefined. the digital output pins (fxd0, cpd0) and status register indicate a non-detection state. at that time, the control register cr and dtmf transmit register dtmft are cleared. ("0" is written) the internal circuits (timer, etc. for each detector) also are reset. after turning on the power, set this pin to "1" to reset the lsi before using this lsi. when this pin is set to "0", the normal operation starts. 11 i x1 x1 and x2 are connected to a 3.579545 mhz crystal. see "oscillation circuit" of the functional description for reference. 12 o x2 13 o clko 3.579545 mhz clock output pin. this pin can drive one ml7005 device.
? semiconductor ml7005 5/24 pin symbol type description 14 i read input pin for processor interface. when ptype is "1" (intel processor mode) : this pin is the read control input pin. when this pin is set to "0", data in the specified register is output to the bus lines (d3 to d0). at that time, cs must be "0". see the figure 4 for processor interface timing. when ptype is "0" (motorola processor mode) : this pin is the clock input pin (equivalent to sclk of the msm7524). when in write mode, data in d3 to d0 is written to the specified register at the falling edge of the read signal. when in read mode, data in the specified register is output to d3 to d0 when the read signal is "1", and d3 to d0 is opened when the read signal is "0". the read signal is not necessarily a periodical signal. see the figure 5 for processor interface timing. 15 i cs chip select input pin for processor interface. when the cs signal is "0", read and write operations are possible. when the cs signal is "1", read and write operations are impossible. 16 i ale input pin for processor interface. when ptype is "1" (intel processor mode) : this pin is the address latch enable input pin. the register address data in d1 to d0 is latched at the falling edge of ale. when ptype is "0" (motorola processor mode) : this pin is the address data input pin (equivalent to ad0 of the msm7524). when this pin is "1", data can be written to the control register (cr) and data can be read from the status register (str). when this pin is "0", data can be written to the dtmf transmit register (dtmft) and data can be read from the dtmf receive register (dtmfr). 17 i wr input pin for processor interface. when ptype is "1" (intel processor mode) : this pin is the write control input. data in the data bus lines (d3 to d0) is written to the specified register. at that time, cs must be "0". when ptype is "0" (motorola processor mode) : this is the signal input pin for controlling the read and write modes (equivalent to r/ w of the msm7524). when this pin is "1", the lsi enters the read mode. when this pin is "0", the lsi enters the write mode. 18 - 21 i/o d3 - d0 4-bit data bus i/o pins for processor interface. when ptype is "1" (intel processor mode), d1 and d0 are also used for addressing. 22 o cpdo digital output pin for cpt detector. when a 400 hz signal is input to the cpdip and cpdim pins, this pin is "1". when the doen register is "0", this pin is fixed at "0". 23 gnd ground pin. 24 o dtgo analog output pin for dtmf signal generator. the tone amplitude is approximately - 9.0 dbm for a low group and approximately - 7.0 dbm for a high group. the transmit signal level can be changed by using the dtai and dtao pins. see the figure 11 for adjusting the transmit signal level. control the on/off of signal transmission by using mfc of the control register.
? semiconductor ml7005 6/24 pin symbol type description 25 i dtai inverting input pin for operational amplifier used for adjusting the transmit output level of the dtmf signal generator. the non-inverting input of this amplifier is internally connected to sg. see the figure 11 for adjusting the transmit signal level. when this amplifier is not used, the dtao pin should be shorted to the dtai pin. 26 o dtao output pin for operational amplifier used for adjusting the transmit output level of the dtmf signal generator. 27 o fxdo digital output pin for fax signal (fx) detector. when a 1300 hz signal is input to the fxdim, this pin is "1". when a call progress tone (cpt) is received (cpd0="1"), this pin is forced to be "0". when the doen register is "0", this pin is fixed at "0". 28 i fxdim inverting input pin for input amplifier used for detecting the fax signal (fx). see the figure 9 for adjusting the receive signal level. when the fx detector is not used, the fxdim pin should be shorted to the fxdio pin. 29 o fxdio output pin for input amplifier used for detecting the fax signal (fx). 30 i cpdip non-inverting input pin for input amplifier used for detecting the cpt. see the figure 8 for adjusting the receive signal level. when the cpt detector is not used, see the figure 10. 31 i cpdim inverting input pin for input amplifier used for detecting the cpt. 32 o cpdio output pin for input amplifier used for detecting the cpt.
? semiconductor ml7005 7/24 absolute maximum ratings recommended operating conditions parameter symbol condition rating unit power supply voltage v dd C0.3 to +7.0 v ta = 25c with respect to gnd input voltage v i C0.3 to v dd + 0.3 storage temperature t stg C55 to +150 c output short current i sht 35 ma short to v dd or gnd power dissipation p d 100 mw parameter symbol condition typ. unit power supply voltage v dd 3.6 v operating temperature range t op c input clock frequency deviation f clk % input clock duty duty % x1, x2 load capacitance c1, c2 pf sg bypass capacitance c3 v dd bypass capacitance c4 m f c5 digital input fall time t if digital ouput load capacitance c dl1 pf c dl2 frequency deviation ppm an external clock is applied to x1 sg - gnd v dd - gnd fcdo, cpdo, d3 to d0 clko +25c 5c 20 min. max. 2.7 5.5 +85 +0.1 60 22 50 40 20 C100 +100 C30 C0.1 40 18 1 10 0.1 digital input rise time t ir ns pd, read , cs , ale, wr , d3 to d0 50 temperature characteristics C30c to +85c C100 +100 equivalent series resistance w 90 load capacitance 16 pf crystal
? semiconductor ml7005 8/24 electrical characteristics dc and digital interface characteristics ac characteristics ac characteristics 1 dtmf signal generator *1 dtrim, dtrip, cpai, dtai, fxdim, cpdip, cpdim *2 dtrio, cpao, cptgo, dtgo, dtao, fxdio, cpdio *3 dtrio, cpao, cptgo, dtgo, dtao, fxdio, cpdio, sg parameter symbol condition or applicable pin typ. unit power supply current i dd1 i dd2 m a digital input voltage v ih v v il digital input current i ih m a i il digital output voltage v oh v v ol v olck 0.06 analog input resistance r in 10 m w power down mode v i = 0 v other than clk0 *1 1 0 0 min. max. 9.0 40 v dd 0.3v dd +10 +10 0.0 0.2 0.7 v dd 0.0 C10 C10 v ohck clko, cl 20pf v dd C 0.06 v dd v dd C 0.2 analog output dc potential v sg v dd /2 sg v dd /2C0.1 v dd /2C0.1 v ao v dd /2 v analog output load resistance r out k w 20 ma 4.0 5.0 *2 *3 i ol = 100 m a i oh = C100 m a v dd = 3 v v dd = 5 v operating mode v dd 0.5 v dd C 0.5 0.0 v i = v dd v dd = 2.7 to 5.5 v (v dd = 2.7 to 5.5 v, ta = C30 to +85c) parameter symbol condition typ. unit dtmf tone transmit amplitude v dttl dbm v dtth f ddt C7.0 out-of-band spurious v s1 pC51 db measured at dtgo with respect to output signal level measured at dtgo min. max. C8.5 C5.5 pC20 v dtdf C9.0 C7.5 C10.5 v s2 pC60 pC40 v s3 pC75 pC60 high group tone low group tone 2.0 3.0 +1.5 1.0 C1.5 v dtth C v dttl to nominal frequency thd dt C40 C23 harmonics - fundamental 4khz to 8khz 8khz to 12khz 12 khz to each 4 khz band tone transmit amplitude ratio tone frequency accuracy total harmonic distortion db % db (v dd = 2.7 to 5.5 v, ta = C30 to +85c) *1 *1 0dbm = 0.775 vrms (for all ac characteristics)
? semiconductor ml7005 9/24 ac characteristics 2 call progress tone (cpt) generator ac characteristics 3 call progress tone (cpt) detector figure 1 cpt detect timing parameter symbol condition typ. unit tone transmit amplitude v cpt C2.5 dbm output frequency f cpt hz 400 min. max. C4 C1 420 380 total harmonic distortion thd cpt db harmonics - fundamental C39 C23 (v dd = 2.7 to 5.5 v, ta = C30 to +85c) parameter symbol condition typ. unit cpt detect amplitude v detcp min. max. C46 C6 dbm 0 C46 C60 f in = 350 to 450 hz at cpdio 2.7 v v dd 5.5 v (v dd = 2.7 to 5.5 v, ta = C30 to +85c) 4.5 v v dd 5.5 v cpt non-detect amplitude v rejcp time to detect t detcp time to reject t rejcp cpt detect delay time t delcp cpt detect hold time t holcp cpt detect frequency f detcp cpt non-detect frequency f retcp ms 10 30 non-detect detect 18 18 30 30 10 10 290 530 hz 450 350 hz see figure 1. ms cpdi cpdo (cpdr) t rejcp t detcp t delcp t holcp
? semiconductor ml7005 10/24 ac characteristics 4 fax signal (fx) detector figure 2 fx detect timing parameter symbol condition typ. unit fx detect amplitude v detfx min. max. C40 C6 dbm 0 C40 C60 f in = 1280 to 1320 hz at fxdio 2.7 v v dd 5.5 v (v dd = 2.7 to 5.5 v, ta = C30 to +85c) 4.5 v v dd 5.5 v fx non-detect amplitude v rejfx time to detect t detfx time to reject t rejfx fx detect delay time t delfx fx detect hold time t holfx fx detect frequency f detfx fx non-detect frequency f rejfx ms 30 65 non-detect detect 50 50 65 65 35 35 1200 1380 hz 1320 1280 hz see figure 2. fxdi fxdo (fxdr) t rejfx t detfx t delfx t holfx
? semiconductor ml7005 11/24 ac characteristics 5 dtmf receiver *1 see the figure 3 for timing. the input level includes the entire range indicated in v detdt1 and v detdt2 . the input frequency includes the entire range indicated in f detdt . parameter symbol condition typ. unit dtmf detect amplitude v detdt1 min. max. C42 C10 dbm 0 C42 C60 per frequency at dtrio 2.7 v v dd 5.5 v (v dd = 2.7 to 5.5 v, ta = C30 to +85c) 4.5 v v dd 5.5 v dtmf non-detect amplitude v rejdt signal repetition time t cycdt0 t cycdt1 time to detect t detdt0 t detdt1 ms 90 60 dttim = "0" dttim = "1" detect frequency f detdt +1.8 C1.8 non-detect frequency f rejdt 3.8 C3.8 +6.0 C6.0 v high group - v low group level twist v twist C12 n/s (n : 0.3 to 3.4 khz) noise to signal ratio v n/s 45 360 to 440 hz dial tone rejection ratio v rejdt % db time to reject t rejdt0 t rejdt1 49 35 acceptable drop out time t brkdt10 t brkdt11 t brkdt20 t brkdt21 interdigit pause time t posdt0 t posdt1 detect delay time t deldt0 t deldt1 detect hold time t holdt0 t holdt1 sp delay time t sp 10 24 21 30 0.4 0.4 3 10 26 12 37 41 24 49 20 15 27 28 24 35 to nominal frequency dttim = "0" dttim = "1" dttim = "0" dttim = "1" dttim = "0" dttim = "1" dttim = "0" dttim = "1" dttim = "0" dttim = "1" dttim = "0" dttim = "1" dttim = "0" dttim = "1" detect non-detect sp = "1" (before output) sp = "0" (during output) 0.6 0.2 1.0 dttim = "1", "0" *1 v detdt2
? semiconductor ml7005 12/24 timing when dtmf is received dtmf receive data sp ain signal t cycdt t detdt t posdt t rejdt t brkdt1 t deldt t sp t holdt t brkdt2 figure 3 timing when dtmf is received t detdt : time to detect when time to detect is the specified value of t detdt or more, the dtmf signal is normally received. t rejdt : time to reject when time to reject is the specified value of t rejdt or less, the input signal is ignored and the sp and dtmf receive data are not output. t posdt : interdigit pause when there is no input signal for the period of t posdt or more, the dtmf receive data and sp are reset. even if the receive data is changed, when interdigit pause time is the value of t posdt or less (including the change without drop out), sp remains at "0" and the dtmf receive data may maintain its initial value. t brkdt1 : acceptable drop out time 1 acceptable drop out time 1 is applied between when the input signal comes and when sp becomes "0". even if there is no input signal for the period of t brkdt1 or less, the sp and dtmf receive data are normally output. t brkdt2 : acceptable drop out time 2 acceptable drop out time 2 is applied when sp is "0" (when receive data is output). even if there is no input signal during signal reception for the period of t brkdt2 or less, sp and dtmf receive data are not reset. t cycdt : signal repetition time signal repetition time should be the specified value of t cycdt or more so that a signal is normally received. t deldt : detect delay time the dtmf receive data is output with a delay of the specified value of t deldt after the input signal appears. t holdt : detect hold time the sp and dtmf receive data outputs stop with a delay of the specified value of t holdt after the input signal disappears. t sp : sp delay time the sp data is output with a delay of the specified value of t sp after the dtmf receive data is output. the dtmf receive data should be latched after detecting the fall of sp .
? semiconductor ml7005 13/24 processor interface charactceristics (intel processor mode) figure 4 processor interface timing (intel processor mode : ptype="1") parameter symbol condition typ. unit address data setup time t al ns address data hold time t la ns min. max. 80 30 ale signal time t ll ns 80 (v dd = 2.7 to 5.5 v, ta = C30 to +85c) chip select setup time before read t crs ns 30 chip select hold time after read t crh ns 30 read data output delay time t rd ns v ol 0.4 v, v oh 3 v dd C 0.4 v 90 180 0 data float time after read t rdf ns 3760 5 read signal time t rw ns 200 chip select setup time before write t cws ns 30 chip select hold time after write t cwh ns 30 wr signal time t ww ns 140 data setup time before write t dw ns 80 data hold time t wd ns 30 ale t ll t ll t rw t ww read wr d0 to d3 cs t al t la t rd t rdf t al t la t dw t wd t crs t crh t cwh t cws address read data address write data
? semiconductor ml7005 14/24 processor interface characteristics (motorola processor mode) figure 5 processor interface timing (motorola processor mode) parameter symbol condition typ. unit read signal period t cyc m s read signal pulse width t hi ns "h" period min. max. 1 200 t lo "l" period 200 (v dd = 2.7 to 5.5 v, ta = C30 to +85c) ale t as ale ? read 80 t ah read ? ale 20 cs t cs cs ? read 80 t ch read ? cs 20 wr t wrs wr ? read 80 t wrh read ? wr 20 d3 to d0 (write) t dws d3 to d0 ? read 80 t dwh read ? d3 to d0 30 d3 to d0 (read) t drd read ? d3 to d0 v ol 0.4 v, v oh 3 v dd C 0.4 v 90 180 0 t drh d3 to d0 ? read 37 60 5 see figure 5 setup time hold time setup time hold time setup time hold time setup time hold time delay time hold time read (clock) ale (address) cs wr (read / write) t hi t lo d3 to d0 data "write" t cyc t dws t dwh t wrh t wrs t ch t cs t ah t as t hi t lo data "read" t cyc t drh t wrh t wrs t ch t cs t ah t as t drd
? semiconductor ml7005 15/24 register description register interface description the ml7005 contains a 4-bit dtmf transmit data register (dtmft), a 4-bit dtmf receive data register (dtmfr), a 4-bit control register (cr), and a 4-bit status register (str). the dtmft and cr registers are for write-only and the dtmfr and str registers are for read-only. when the ptype pin is "1", accessing the registers is possible in the intel processor mode. when the ptype pin is "0", accessing the registers is possible in the motorola processor mode. in the intel processor mode (ptype="1"), when cs is "0", data can be written to the dtmft and cr registers by fetching data from d3 to d0 at the rising edge of the wr signal. when cs is "0", the contents of dtmfr and str can be transferred to d3 to d0 by setting read to "0". in the motorola processor mode (ptype="0"), when cs and wr are "0", data can be written to the dtmft and cr registers by fetching d3 to d0 data and ale at the falling edge of read . when cs is "0" and wr is "1", the contents of dtmfr and str are transferred to d3 to d0 by latching ale at the rising edge of read . when the pd pin is set to "1" the dtmft and cr registers are reset. table 1 outline of registers note: the contents of the dtmft and cr registers cannot be read. table 2 register names register name accessing (address) in intel processor mode description accessing in motorola processor mode writing to dtmft wr ale d0 d1 reading from dtmfr 0 1 0 0 0 1 0 0 dtmft dtmfr writing to cr 0 1 0 1 cr reading from str 1 1 1 1 str register name d0 d1 d2 d3 dtt0 dtr0 dtt1 dtr1 dtt2 dtr2 dtt3 dtr3 dtmft dtmfr mfc doen dttim cpgc cr detf cpdr fxdr sp str
? semiconductor ml7005 16/24 dtmft and dtmfr registers 16 kinds of dtmf transmit signals can be determined by setting the dtmft register. 16 kinds of dtmf receive signals can be monitored from the dtmfr register. the table 3 shows the dtmf signal codes. even if the dtmf transmit code is changed while the dtmf signal is being transmitted (mfc="1"), the output frequency is not changed. table 3 dtmf signal code list high group signal (hz) low group signal (hz) 1209 1336 697 697 1477 697 1209 770 digit 1 2 3 4 dtt0 dtr0 1 0 1 0 dtt1 dtr1 0 1 1 0 dtt2 dtr2 0 0 0 1 dtt3 dtr3 0 0 0 0 1336 770 5 1 0 1 0 1477 770 6 0 1 1 0 1209 852 7 1 1 1 0 1336 852 8 0 0 0 1 1477 852 9 1 0 0 1 1336 941 0 0 1 0 1 1209 941 * 1 1 0 1 1477 941 # 0 0 1 1 1633 697 a 1 0 1 1 1633 770 b 0 1 1 1 1633 852 c 1 1 1 1 1633 941 d 0 0 0 0
? semiconductor ml7005 17/24 control register cr bit no. name description d3 cpgc this bit is used to control the on/off of call progress tone transmitting. "0" : the gptgo output is off and the sg level is output. "1" : the gptgo output is on and cpt is output. d2 dttim this bit is used to control the detect time of dtmf receiver. "0" : normal detect "1" : high-speed detect when there is enough time, set to the normal detect mode (dttim = "0") because the high-speed detect mode sometimes causes erroneous detection by noise or voice signal. d1 doen this bit is used to control the call progress tone detector and fx detector. "0" : the cpdo and fxdo output pins and cpdr and fxdr registers are fixed to "0". "1" : the cpdo and fxdo output pins and cpdr and fxdr registers become valid. d0 mfc this bit is used to control the on/off of dtmf transmit output. "0" : the dtgo output is off and the sg level is output. "1" : the dtgo output is on and the dtmf signal is output. d3 cpgc d2 dttim d1 doen d0 mfc
? semiconductor ml7005 18/24 status register str bit no. name description d3 sp this bit is used to indicate whether the dtmf receive signal is being received. "0" : indicates that the valid dtmf signal is being received. "1" : indicates that the dtmf signal is not being received. d2 fxdr this bit is used to indicate whether the fax signal (fx) is being received. "0" : indicates that the fax signal (fx) is not being received. "1" : indicates that the valid fax signal (fx: 1300 hz) is being received. when a call progress tone is received (cpdo="1"), this bit is forced to be "0". when the doen register is "0", this bit also is fixed at "0". this bit has the same function as that of the fxdo. d1 cpdr this bit is used to indicate whether the call progress tone is being received. "0" : indicates that the call progress tone is not being received. "1" : indicates that the valid call progress tone (400 hz) is being received. when the doen register is "0", this bit is fixed at "0". this bit has the same function as that of the cpdo pin. d0 detf this is a flag to indicate that a detector has changed its status from a non-detect state to a detect state. this bit is "1" when: (1) sp is changed from "1" to "0", (2) fxdr is changed from "0" to "1", or (3) cpdr is changed from "0" to "1". this bit remains "0" even if a 1300 hz or 400 hz signal is input, because the fxdr and cpdr are fixed at "0" when the doen regsiter is "0". when the processor has read the status register, this bit is reset to "0". when the processor does not read the status register after a signal is detected, this bit is "0" after the detected signal disappears. d3 sp d2 fxdr d1 cpdr d0 detf
? semiconductor ml7005 19/24 functional description oscillation circuit the x1 and x2 should be connected by a 3.579545 mhz crystal. when the load capacitance of the crystal is 16pf, x1 and gnd should be connected by a 20 pf capacitor, and x2 and gnd also should be connected by a 20 pf capacitor. if necessary, an external clock should be input to x1 via a 1000 pf capacitor, and x2 should be left open. figure 6 crystal connection figure 7 external clock connection dtmf receiver, cpt detector input level adjustment adjust the input level according to the method shown in the figure 8. determine the value of a usable resistor so that the levels of the outputs (dtio, cpdio) of each amplifier at a maximum input level are less than the maximum detect level described in the ac characteristics. x1 x2 c1 3.579545mhz c2 x1 x2 3.579545mhz figure 8 dtmf, cpt input level adjustment + C r a r c r b dtrio dtrim ca in dtrip (cpdim) (cpdip) (cpdio) sg r a 3 100 k w r b , r c 3 50 k w ca 3 0.1 m f gain = 1 + r b r c 10 C + r d dtrip ca in dtrim (cpdip) (cpdim) sg gain = r e r d 10 r e dtrio (cpdio)
? semiconductor ml7005 20/24 figure 9 fx input level adjustment processing the input pin when the dtmf receiver and cpt detector are not used process the input pin according to the method shown in the figure 10. C + r f c8 in fxdim gain = r g r f 10 r g fxdio fx detector input level adjustment adjust the input level according to the method shown in the figure 9. determine the value of a usable resistor so that the output level of fxdio is less than the maximum detect level described in the ac characteristics. figure 10 processing the unused input pin C + dtrip (cpdip) dtrim (cpdim) sg dtrio (cpdio)
? semiconductor ml7005 21/24 figure 11 analog output level adjustment concurrent operation of 4 functions the dtmf signal generator, dtmf signal detector, call progress tone generator, and call progress tone detector can operate concurrently. when both the dtmf signal generator and call progress tone generator operate concurrently, the dtmf signal sometimes cannot be detected if the receive level of the dtmf signal is less than -36 dbm. adjusting the analog output level adjust the analog output level according to the method shown in the figure 11. r i /r h 1.6 is always required when v dd 3 4.5 v. in the case of r i /r h > 1, if r i /r h = a, the maximum analog output load resistance is 20*a (k w ). if v dd is less than 4.5 v, r i /r h 1 is required. C + dtai (cpai) out gain = r i r h r h dtgo (cpdgo) r i dtao (cpao) generator
? semiconductor ml7005 22/24 register settings for each mode an example of register settings for each mode is shown below. table 4 register setting mode power on dtmf detect (high speed) cpt detect description (1) wait until power supply is stabilized (2) pd pin = "1" (internal circuit is reset) (3) wait 200 m s or more (4) pd pin = "0" (5) cr setting (1) detect timing setting (2) str monitoring (when not detected) (3) str monitoring (when detected) (4) dtmf receive data reading (5) str monitoring (when detected and after reading str) (6) str monitoring (after making the input signal off) (1) cpt detect enable setting (2) str monitoring (when not detected) (3) str monitoring (when detected) address in intel processor mode d1, d0 10 10 11 11 01 11 11 10 11 11 ale wr motorola processor mode d3 d2 d1 d0 active register 1 1 1 1 0 1 1 1 1 1 0 0 1 1 1 1 1 0 1 1 x 0 1 0 x 0 1 0 1 1 x 1 0 0 x 0 0 0 0 0 x 0 0 0 x 0 0 1 0 1 x 0 0 1 x 0 0 0 0 1 cr cr str str dtmfr str str cr str str (4) str monitoring (when detected and after reading str) 11 111010 str dtmf transmit (1) dtmf transmit data setting 00 0 0 x x x x dtmft (2) dtmf transmit on 10 1 00001 cr (3) wait transmit on time (4) dtmf transmit off 10 1 00000 cr (5) wait transmit off time (6) to transmit next data, return to (1) cpt transmit (1) cpt transmit on 10 1 01000 cr (2) wait transmit on time (3) cpt transmit off 10 1 00000 cr
? semiconductor ml7005 23/24 application circuit example note : indicates connection to the sg pin. 1 r2 c6 dtmf input r1 2 dtrio dtrim 3 4 dtrip sg c3 ml7005 8 9 ptype v dd c4 +2.7 to 5.5 v c5 + C c1 c2 3.579545 mhz cpdio cpdim cpdip fxdio fxdim fxdo dtao dtai dtgo gnd cpdo d0 d1 d2 d3 wr 32 31 30 28 27 26 25 24 23 22 21 20 19 18 17 r3 r4 r5 r6 c7 c8 cpt input fx input to mpu cpao cpai cptgo 5 6 7 10 pd 11 x1 12 x2 13 clko 14 read 15 cs 16 ale 29
? semiconductor ml7005 24/24 (unit : mm) package dimensions notes for mounting the surface mount type package the sop, qfp, tsop, tqfp, lqfp, soj, qfj (plcc), shp, and bga are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. therefore, before you perform reflow mounting, contact okis responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). ssop32-p-430-1.00-k package material lead frame material pin treatment solder plate thickness package weight (g) epoxy resin 42 alloy solder plating 5 m m or more 0.60 typ. mirror finish
notice 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third partys industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. no responsibility is assumed by us for any infringement of a third partys right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. 9. ms-dos is a registered trademark of microsoft corporation. copyright 1999 oki electric industry co., ltd. printed in japan e2y0002-29-62

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